1. Field of the Invention
The present invention relates generally to high-speed digital data transmission systems and more specifically to a circuit and method for data recovery for non-uniformly spaced data.
2. Description of the Background Art
In conventional digital communication systems, electronic information is transferred between a transmitting unit and a receiving unit over a communications channel, such as a transmission line. The electronic information is commonly transmitted in the form of data bits, with each bit being a binary xe2x80x9c0xe2x80x9d (hereinafter simply xe2x80x9c0xe2x80x9d) or a binary xe2x80x9c1xe2x80x9d (hereinafter simply xe2x80x9c1xe2x80x9d). The xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d values can, for example, represent low and high voltages, respectively.
The transferred electronic information is further characterized by a fundamental bit rate, i.e., the clock frequency of the data bits. In synchronous transmission typically used in computer-to-computer communication, for example, the receiving unit determines the clock frequency of the transmitting unit (e.g., for decoding purposes) by deriving a clock signal from timing information of the transmitted data bits. This process is known as clock recovery. The recovered clock signal enables the receiving unit to optimally sample the received digitally encoded electronic information during the decoding process.
Clock recovery circuits are commonly employed, for example, in conjunction with Local Area Networks (LANs) and point-to-point communication links. A conventional clock recovery circuit typically employs phase-locked loops (PLLs). A typical PLL has a voltage-controlled-oscillator (VCO) whose phase will lock onto a frequency component of the PLL input signal from the destination clock generator. The PLL also has a phase detector for comparing the phase of the VCO with the phase of the PLL input signal, and for developing a voltage proportional to the phase differential, which commonly is referred to as a xe2x80x9cphase error.xe2x80x9d This voltage is filtered and applied as a control voltage to the VCO to adjust the VCO""s frequency. Due to negative feedback, the phase error is driven to a preferably small value, and the VCO""s frequency consequently becomes equal to the PLL input frequency. PLL circuits are further shown and described in Best, R. E., Phase-Locked Loops Theory, Design, and Application, McGraw-Hill Book Company, New York, N.Y. (1993); Razavi, Behzad, Monolithic Phase-locked Loops and Clock Recovery Circuits, Theory and Design, IEEE Press, New York, N.Y. (1996); Gardner, Floyd M., Phaselock Techniques, John Wiley and Sons (1979); and Haung, H. M., Banatao, D., Perlegos, G., Wu, T. C., and Chiu, T. L., A CMOS Ethernet Serial Interface Chip, IEEE International Solid-State Circuits Conference Digest (1984).
Data and clock recovery circuits using the xe2x80x9cone-shotxe2x80x9d method are shown and described in Bell, A. G., Borriello, G., A Single Chip NMOS Ethernet Controller, IEEE International Solid-State Circuits Conference Digest (1983), which is incorporated herein by reference. Clock and data recovery circuits are also shown and described in U.S. Pat. No. 5,056,118 issued to Sun on Oct. 8, 1991; U.S. Pat. No. 5,103,466 issued to Bazes on Apr. 7, 1992; in U.S. Pat. No. 5,164,966 issued to Hershberger on Nov. 17, 1992; U.S. Pat. No. 4,853,943 issued to Laws on Aug. 1, 1989; and U.S. Pat. No. 4,841,257 issued to Morrison et al. on Jun. 20, 1989.
Various analog approaches exist for data and clock recovery. For example, in U.S. Pat. No. 5,124,669 to Palmer et al., a clock recovery circuit using a PLL is shown and described. A one-shot circuit is coupled to the PLL to enable the phase detector when the data stream does not consist of uniformly spaced pulses. Without a one-shot circuit, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data pulse edge and the next clock pulse edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled at one half of a clock period before the data edge. By doing this, the data edge can shift up to one half of a clock period before the phase detector generates an incorrect error signal. If the data edge is shifted further than one half of a clock period, then the data edge is compared to a different rising clock edge and the detector generates an error. The one-shot circuit has been designed to generate a delayed data signal whose rising edge is used to enable the phase detector, and whose falling edge is compared with the clock edge for disabling the phase detector.
However, the circuit of Palmer would cause erroneous data and/or clock recovery if a data stream edge (transition) does not occur within a significant time length, such as 60 bit times. In addition, PLLs in conventional data and clock recovery systems tend to drift if an edge-starved pattern (a period of time when the number of data edges is far below the expected or average number of edges) appears in the data stream. This drift causes the PLL to become out of phase with the source clock phase and frequently results in erroneous data recovery.
Traditional PLLs tend to drift in edge-starved situations due to either too much gain resulting in too much or too little gain resulting in too slow a response. In the prior art, edge-starvation has been dealt with by reducing the loop gain and accepting a slower response in order to avoid the instability of over-correction resulting from high loop gain.
Additionally, wobble (where high jitter levels exist in the data and the PLL gain cannot be sufficiently controlled) can occur in analog PLL approaches to clock and data recovery. Jitter is typically a result of instantaneous noise injection in the communications system, or a result of transmission cable imperfections, or a result of source clock imperfections, and/or a result of other electrical behavioral characteristics. Conventional PLL-based clock/data recovery systems tend to lock on the jittered bits and accordingly perform unnecessary phase adjustments. This tendency causes a traditional PLL to go out of phase with the source clock phase during periods of edge-starvation.
Thus, what is needed is a novel data and clock recovery circuit and method that will overcome the foregoing deficiencies.
An object of the present invention is to provide a clock frequency tracking mechanism which will more closely track the actual clock frequency used in a network. The invention has the advantage of using the PLL with a reduced sensitivity that meets the needs of tracking the clock frequency of a network.
The shared data and clock recovery circuit includes a source clock, a destination clock, a clock synthesizer, for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, a counter/accumulator for detecting the time occurrences and total number of edges, and for performing a weighted averaging calculation and outputting a signal reflecting the weighted averaging to select one of the different phases, and a circuit to track and digitally store the parts-per-million (PPM) frequency difference between the source clock and the destination clock.